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Silicon Labs /Series0 /EZR32HG /EZR32HG320F64R61 /VCMP /CTRL

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Interpret as CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EN)EN 0 (INACTVAL)INACTVAL 0 (HYSTEN)HYSTEN 0 (4CYCLES)WARMTIME 0 (IRISE)IRISE 0 (IFALL)IFALL 0BIASPROG 0 (HALFBIAS)HALFBIAS

WARMTIME=4CYCLES

Description

Control Register

Fields

EN

Voltage Supply Comparator Enable
INACTVAL

Inactive Value
HYSTEN

Hysteresis Enable
WARMTIME

Warm-Up Time

0 (4CYCLES): 4 HFPERCLK cycles

1 (8CYCLES): 8 HFPERCLK cycles

2 (16CYCLES): 16 HFPERCLK cycles

3 (32CYCLES): 32 HFPERCLK cycles

4 (64CYCLES): 64 HFPERCLK cycles

5 (128CYCLES): 128 HFPERCLK cycles

6 (256CYCLES): 256 HFPERCLK cycles

7 (512CYCLES): 512 HFPERCLK cycles
IRISE

Rising Edge Interrupt Sense
IFALL

Falling Edge Interrupt Sense
BIASPROG

VCMP Bias Programming Value
HALFBIAS

Half Bias Current

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data